An image sensor conventionally comprises a matrix of pixels. Each pixel delivers an electrical signal whose level depends on the quantity of light received.
Traditionally, the processing chain for the signal arising from a pixel comprises several signal amplification stages. These amplification stages are supplied by a current source and are in general all linked to a common ground.
In image sensors, in a general manner, in order to read the information signal arising from the matrix of pixels, a difference is derived between two output voltage levels of a pixel occurring successively over time, the difference between these two voltage levels being proportional to the quantity of light received by the photodiode diode.
The output voltage of the pixel being referenced to the ground of the circuit, it is desirable that the ground potential remains as stable as possible over time: in particular, any fluctuation in the ground potential between the times at which the output voltage levels considered are measured, mars the difference of these levels through an error which may not be possible to correct subsequently, and which might degrade the quality of the image obtained.
Fluctuations in ground potential occur when the current flowing in the ground is not constant: it is therefore necessary to take care that this current remains as constant as possible. A solution for preventing a degradation in the reading of the information signals of an image sensor can consist in limiting the output voltage of the first amplification stage of the sensor so as to keep the current injected into the ground constant.
FIG. 1 schematically illustrates an example for voltage-limiting the output signal of an amplification stage of an image sensor. An example of an amplification stage RA connected to a limiting device LIM has been represented in FIG. 1. The amplification stage RA comprises a transistor N1 of NMOS type connected between an output terminal OUT intended to receive a current source SC and a reference terminal Vref connected to the ground potential.
The limiting device LIM comprises a transistor T1 of PMOS type mounted between the output terminal OUT of the amplification stage RA and the reference terminal Vref. Furthermore, the gate of the transistor T1 is controlled with the aid of a constant voltage Vclamp0. In this configuration, when the voltage of the signal delivered at the output OUT is greater than a certain threshold, which depends on the value of the control voltage Vclamp0 and the characteristics of the transistor T1 of PMOS type, the latter turns on, thus diverting the current towards the reference terminal Vref, here ground. The signal is then said to be voltage-limited. Conversely, when the voltage of the signal is below this threshold, the transistor T1 of PMOS type is off, no current flows in the said transistor T1.
Also depicted in FIG. 1 is the current Ip provided by the current source SC, the current Idry which passes through the transistor N1 of the amplification stage RA, and the current Iclp which passes through the transistor T1 of the limiting device LIM.
Represented in FIG. 2 are the curves of the main currents which pass through the system described above in FIG. 1 as a function of the voltage VOUT of the signal delivered to the output OUT of the amplification stage RA. The curve Cldry represents the current Idry which passes through the transistor N1 of the amplification stage RA, the curve CIclp represents the current Iclp which passes through the transistor T1 of the limiting device LIM and the curve CIp represents the current Ip provided by the current source SC (Ip=Idrv+Iclp).
Also represented in FIG. 2 is the voltage span P1 necessary in order for the transistor T1 of the limiting device LIM to divert the entire current of the current source SC. This voltage span P1 extends beyond the voltage Vclamp0+Vt, where Vt is the threshold voltage of the transistor T1. In general, this voltage span is of the order of 1 Volt.
In this prior art architecture, the voltage span P1 necessary in order for the transistor T1 to absorb the entire current of the current source SC is non-negligible and may give rise to a variation in current flowing in ground.
Indeed, if the voltage VOUT increases, the voltage across the terminals of the current source SC decreases and this may cause the current of this source to reduce, and therefore create a variation in the ground potential. Furthermore, when the voltage margin across the terminals of the current source SC decreases, the current Ip provided by the current source SC may drop when the transistor T1 of the limiting device LIM turns on.
It is therefore necessary to guarantee a minimum voltage across the terminals of the current source SC so that this current source SC can operate on the one hand, and to guarantee a sufficient voltage across the terminals of the current source SC so that the current provided by the said source is constant, on the other hand, in order to prevent any current variation at ground.